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cmos, low voltage, 4 dual spst switches in 3 mm 2 mm lfcsp adg721/adg722/adg723 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004-2011 analog devices, inc. all rights reserved. features 1.8 v to 5.5 v single supply 4 (max) on resistance low on resistance flatness ?3 db bandwidth >200 mhz tiny package options 8-lead msop 3 mm 2 mm lfcsp (a grade) fast switching times t on , 20 ns t off , 10 ns low power consumption (<0.1 w) ttl/cmos compatible applications usb 1.1 signal switching circuits cell phones pdas battery-powered systems communication systems sample hold systems audio signal routing video switching mechanical reed relay replacement functional block diagrams adg721 in1 d2 s2 s1 d1 in2 00045-001 adg722 in1 d2 s2 s1 d1 in2 00045-002 figure 1. figure 2. adg723 switches shown for a logic "0" input in1 d2 s2 s1 d1 in2 00045-003 figure 3. general description the adg721, adg722, and adg723 are monolithic cmos spst switches. these switches are designed on an advanced submicron process that provides low power dissipation yet gives high switching speed, low on resistance, and low leakage currents. the devices are packaged in both a tiny 3 mm 2 mm lfcsp and an msop, making them ideal for space-constrained applications. the adg721, adg722, and adg723 are designed to operate from a single 1.8 v to 5.5 v supply, making them ideal for use in battery-powered instruments and with the new generation of dacs and adcs from analog devices, inc. the adg721, adg722, and adg723 contain two independent single-pole/single-throw (spst) switches. the adg721 and adg722 differ only in that both switches are normally open and normally closed, respectively. in the adg723, switch 1 is normally open and switch 2 is normally closed. each switch of the adg721, adg722, and adg723 conducts equally well in both directions when on. the adg723 exhibits break-before-make switching action. product highlights 1. 1.8 v to 5.5 v single-supply operation. 2. ver y low r on (4 max at 5 v, 10 max at 3 v). 3. low on resistance flatness. 4. ?3 db bandwidth >200 mhz. 5. low power dissipation. cmos construction ensures low power dissipation. 6. 8-lead msop and 3 mm 2 mm lfcsp.
adg721/adg722/adg723 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagrams............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? esd caution.................................................................................. 5 ? pin configuration and pin descriptions....................................... 6 ? terminology .......................................................................................7 ? typical performance characteristics ..............................................8 ? test circuits..................................................................................... 10 ? applications..................................................................................... 12 ? adg721/adg722/adg723 supply voltages ....................... 12 ? on response vs. frequency ...................................................... 12 ? off isolation ................................................................................ 12 ? outline dimensions ....................................................................... 13 ? ordering guide .......................................................................... 14 ? revision history 4/11rev. c to rev. d changes to ordering guide .......................................................... 14 1/11rev. b to rev. c changes to table 4............................................................................ 6 changes to ordering guide .......................................................... 14 2/07rev. a to rev. b updated format..................................................................universal changes to specifications ................................................................ 3 changes to absolute maximum ratings ....................................... 5 change to figure 4 ........................................................................... 6 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 13 3/04rev. 0 to rev. a additions to applications................................................................ 1 changes to ordering guide ............................................................ 4 updated outline dimensions ....................................................... 10
adg721/adg722/adg723 rev. d | page 3 of 16 specifications v dd = 5 v 10%, gnd = 0 v. all specifications ?40c to +85c, unless otherwise noted. table 1. a, b grade 1 parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 2.5 typ v s = 0 v to v dd , i s = ?10 ma 4 5 max see figure 12 on resistance match between channels, ?r on 0.3 typ v s = 0 v to v dd , i s = ?10 ma 1.0 max on resistance flatness, r flat(on) 0.85 typ v s = 0 v to v dd , i s = ?10 ma 1.5 max leakage currents C a grade v dd = 5.5 v source off leakage, i s (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v, see figure 13 drain off leakage, i d (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v, see figure 13 channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 1 v or v s = v d = 4.5 v, see figure 14 leakage currents C b grade v dd = 5.5 v source off leakage, i s (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v 0.25 0.35 na max test circuit 2 drain off leakage, i d (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v 0.25 0.35 na max see figure 13 channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 1 v or v s = v d = 4.5 v 0.25 0.35 na max see figure 14 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max dynamic characteristics 2 t on 14 ns typ r l = 300 , c l = 35 pf 20 ns max v s = 3 v, see figure 15 t off 6 ns typ r l = 300 , c l = 35 pf 10 ns max v s = 3 v, see figure 15 break-before-make time delay, t d (adg723 only) 7 ns typ r l = 300 , c l = 35 pf 1 ns min v s1 = v s2 = 3 v, see figure 16 charge injection 2 pc typ v s = 2 v, r s = 0 , c l = 1 nf, see figure 17 off isolation ?60 db typ r l = 50 , c l = 5 pf, f = 10 mhz ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 18 channel-to-channel crosstalk ?77 db typ r l = 50 , c l = 5 pf, f = 10 mhz ?97 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 19 bandwidth ?3 db 200 mhz typ r l = 50 , c l = 5 pf, see figure 20 c s (off) 7 pf typ c d (off) 7 pf typ c d , c s (on) 18 pf typ power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5 v 1.0 a max 1 temperature range: a, b grades, ?40c to +85c. all specifications apply to both grades unless otherwise stated. 2 guaranteed by design; not subject to production test.
adg721/adg722/adg723 rev. d | page 4 of 16 v dd = 3 v 10%, gnd = 0 v. all specifications ?40c to +85c, unless otherwise noted. table 2. a, b grades 1 parameter +25c ? 40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 6.5 typ v s = 0 v to v dd , i s = ?10 ma 10 max see figure 12 on resistance match between channels, ?r on 0.3 typ v s = 0 v to v dd , i s = ?10 ma 1.0 max on resistance flatness, r flat(on) 3.5 typ v s = 0 v to v dd , i s = ?10 ma leakage currents C a grade v dd = 3.3 v source off leakage, i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v, see figure 13 drain off leakage, i d (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v, see figure 13 channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 1 v or 3 v, figure 14 leakage currents C b grade v dd = 3.3 v source off leakage, i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v 0.25 0.35 na max see figure 13 drain off leakage, i d (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v 0.25 0.35 na max see figure 13 channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 1 v or 3 v 0.25 0.35 na max see figure 14 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max dynamic characteristics 2 t on 16 ns typ r l = 300 , c l = 35 pf 24 ns max v s = 2 v, see figure 15 t off 7 ns typ r l = 300 , c l = 35 pf 11 ns max v s = 2 v, see figure 15 break-before-make time delay, t d (adg723 only) 7 ns typ r l = 300 , c l = 35 pf 1 ns min v s1 = v s2 = 2 v, see figure 16 charge injection 2 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf, see figure 17 off isolation ?60 db typ r l = 50 , c l = 5 pf, f = 10 mhz ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 18 channel-to-channel crosstalk ?77 db typ r l = 50 , c l = 5 pf, f = 10 mhz ?97 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 19 bandwidth ?3 db 200 mhz typ r l = 50 , c l = 5 pf, see figure 20 c s (off) 7 pf typ c d (off) 7 pf typ c d , c s (on) 18 pf typ power requirements v dd = 3.3 v i dd 0.001 a typ digital inputs = 0 v or 3 v 1.0 a max 1 temperature range: a, b grades, ?40c to +85c. all specifications apply to both grades unless otherwise stated. 2 guaranteed by design; not subject to production test.
adg721/adg722/adg723 rev. d | page 5 of 16 absolute maximum ratings t a = 25c unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v analog, digital inputs 1 ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d 30 ma operating temperature range industrial (a, b grade) ?40c to +85c storage temperature range ?65c to +150c junction temperature +150c 8-lead msop ja thermal impedance 206c/w jc thermal impedance 44c/w 8-lead lfcsp (4-layer board) ja thermal impedance 1 50.8c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c lead-free temperature, soldering ir reflow, peak temperature 260c (+0/?5c) time at peak temperature 10 sec to 40 sec esd 2 kv 1 assumes exposed paddle is tied to ground. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg721/adg722/adg723 rev. d | page 6 of 16 pin configuration and pin descriptions 8 7 6 5 1 2 3 4 s1 d1 in2 gnd in1 d2 s2 v dd adg721/ adg722/ adg723 top view (not to scale) 00045-004 notes 1. exposed paddle of lfcsp should be tied to ground. figure 4. pin configuration table 4. pin function descriptions pin no. neonic descriptions 1 s1 source pin 1. may be an input or an output. 2 d1 drain pin 1. may be an input or an output. 3 in2 logic control input for switch s2 ? d2. 4 gnd ground (0 v) reference. 5 s2 source pin 2. may be an input or an output. 6 d2 drain pin 2. may be an input or an output. 7 in1 logic control input for switch s1 ? d1. 8 v dd positive power supply input. table 5. truth table (adg721/adg722) adg721 in adg722 in sitch conition 0 1 off 1 0 on table 6. truth table (adg723) logic sitch 1 sitch 2 0 off on 1 on off
adg721/adg722/adg723 rev. d | page 7 of 16 terminology v dd most positive power supply potential. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. r on on resistance match between any two channels, that is, r on max ? r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on the d and s terminals. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 90% points of both switches, when switching from one address state to another (adg723 only). crosstalk a measure of unwanted signal that is the result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. charge injection a measure of the glitch impulse transferred during switching.
adg721/adg722/adg723 rev. d | page 8 of 16 typical performance characteristics 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5.5 6.0 r on ( ? ) v d or v s ? drain or source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a = 25c v dd = 2.7v v dd = 4.5v v dd = 3.0v v dd = 5.0v 00045-005 figure 5. on resistance as a function of v d (v s ), single supplies 6 5 4 3 2 1 0 v d or v s ? drain or source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = 3v r on ( ? ) +85c +25c ?40c 00045-006 figure 6. on resistance as a function of a v d (v s ) for different temperatures, v dd = 3 v 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 6.0 5.5 5.0 4.5 v d or v s ? drain or source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd = 5v r on ( ? ) +85c +25c ?40c 00045-007 figure 7. on resistance as a function of v d (v s ) for different temperatures, v dd = 5 v frequency (hz) 1 m 100 10 1 100n 10n 1n i supply (a) 10 100 1k 10k 100k 1m 10m v dd = 5v 0 0045-008 figure 8. supply current vs. input switching frequency frequency (hz) ? 30 off isolation (db) ?40 ?50 ?60 ?70 ?80 ?90 ?100 v dd = 3v, 5v 10k 100k 1m 10m 100m 00045-009 figure 9. off isol ation vs. frequency frequency (hz) ? 30 crosstalk (db) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m v dd = 3v, 5v 00045-010 figure 10. crosstalk vs. frequency
adg721/adg722/adg723 rev. d | page 9 of 16 ? 6 on response (db) ?7 ?8 ?9 ?10 ?11 ?12 frequency (hz) 10k 100k 1m 10m 100m v dd = 5v 1k 100 00045-011 figure 11. on response vs. frequency
adg721/adg722/adg723 rev. d | page 10 of 16 test circuits v1 i ds sd r on = v1/i ds v s 0 0045-012 figure 12. on resistance a a v s i s (off) i d (off) v d 00045-013 sd figure 13. off leakage a v s i d (on) v d 00045-014 sd figure 14. on leakage in gnd adg721 adg722 50% 50% 50% 50% 90% 90% t off t on v out v in v in v out v dd v dd v s 0.1f r l 300? c l 35pf 00045-015 sd figure 15. switching times in1, in2 gnd 90% 90% 0v 0v 0v 50% 50% 90% 90% t d t d v out1 v in v out2 v dd v s1 0.1f r l2 300 ? c l2 35pf v s2 v dd r l1 300 ? c l1 35pf v out1 v out2 v in 00045-016 s1 d1 s2 d2 figure 16. break-before-make time delay, t d (adg723 only) sw on sw off v out v in ? v out v dd c l 1nf q inj = c l ? v out v out r s v s 00045-017 in gnd v dd sd figure 17. charge injection
adg721/adg722/adg723 rev. d | page 11 of 16 v in v dd 0.1f r l 50 ? v out v s 00045-018 in gnd v dd sd figure 18. off isolation v in v dd 0.1f r l 50? v out v s 00045-019 in gnd v dd sd figure 19. channel-to-channel crosstalk nc channel-to-channel crosstalk = 20 log | v s /v out | v in1 v dd 0.1f r l 50? v out v s 50 ? v in2 00045-020 v dd gnd sd sd figure 20. bandwidth
adg721/adg722/adg723 rev. d | page 12 of 16 applications the adg721/adg722/adg723 belong to a new family of analog devices cmos switches. this series of general-purpose switches has improved switching times, lower on resistance, higher bandwidths, low power consumption, and low leakage currents. adg721/adg722/adg723 supply voltages functionality of the adg721/adg722/adg723 extends from a 1.8 v to a 5.5 v single supply, which makes it ideal for battery- powered instruments, where important design parameters are power efficiency and performance. it is important to note that the supply voltage affects the input signal range, the on resistance, and the switching times of the part. the typical performance characteristics and the specifications clearly show the effects of the power supplies. for v dd = 1.8 v, on resistance is typically 40 over the temperature range. on response vs. frequency figure 21 illustrates the parasitic components that affect the ac performance of cmos switches (the switch is shown surrounded by a box). additional external capacitances further degrade some aspects of performance. these capacitances affect feedthrough, crosstalk, and system bandwidth. s d c d r load v out v in c ds c load r on 00045-021 figure 21. switch represented by equivalent parasitic components the transfer function that describes the equivalent diagram of the switch ( figure 21 ) is of the form (a)s, as shown in the following equation: () () ? ? ? ? ? ? ? ? + + = 1 1 )( tt on dson t rcrs crs rsa where: c t = c load + c d + c ds r t = r load /(r load + r on ) the signal transfer characteristic is dependent on the switch channel capacitance, c ds . this capacitance creates a frequency zero in the numerator of the transfer function a(s). because the switch on resistance is small, this zero usually occurs at high frequencies. the bandwidth is a function of the switch output capacitance combined with c ds and the load capacitance. the frequency pole corresponding to these capacitances appears in the denominator of a(s). the dominant effect of the output capacitance, c d , causes the pole breakpoint frequency to occur first. therefore, in order to maximize bandwidth, a switch must have a low input and output capacitance and low on resistance (see figure 11 ). off isolation off isolation is a measure of the input signal coupled through an off switch to the switch output. the capacitance, c ds , couples the input signal to the output load, when the switch is off, as shown in figure 22 . s d c d r load v out v in c ds c load 00045-022 figure 22. off isolation is affected by external load resistance and capacitance the larger the value of c ds , the larger the value of feedthrough produced. figure 9 illustrates the drop in off isolation as a function of frequency. from dc to roughly 1 mhz, the switch shows better than ?80 db isolation. up to frequencies of 10 mhz, the off isolation remains better than ?60 db. as the frequency increases, more and more of the input signal is coupled through to the output. off isolation can be maximized by choosing a switch with the smallest c ds possible. the values of load resistance and capacitance also affect off isolation because they contribute to the coefficients of the poles and zeros in the transfer function of the switch when open. ( ) () () ? ? ? ? ? ? ? ? +++ = 1 )( ds d load load ds load cccrs crs sa
adg721/adg722/adg723 rev. d | page 13 of 16 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 23. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0 81806- a coplanarity 0.08 0.50 0.40 0.30 0.20 min 0.05 max 0.02 nom 0.15 ref 0.50 pin 1 indicator exposed pad bottom view top view 0.30 0.25 0.20 0.80 0.75 0.70 seating plane 3.00 bsc side view 1 4 8 5 2.00 bsc index area 1.90 1.80 1.65 1.75 1.65 1.50 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 24. 8-lead lead frame chip scale package [lfcsp_wd] 3 mm 2 mm body, very very thin, dual lead (cp-8-4) dimensions shown in millimeters
adg721/adg722/adg723 rev. d | page 14 of 16 ordering guide model 1 temperature range package description package option branding 2 adg721brm ?40c to +85c 8-lead msop rm-8 s6b adg721brm-reel ?40c to +85c 8-lead msop rm-8 s6b adg721brm-reel7 ?40c to +85c 8-lead msop rm-8 s6b adg721brmz ?40c to +85c 8-lead msop rm-8 #s6b adg721brmz-reel ?40c to +85c 8-lead msop rm-8 #s6b adg721brmz-reel7 ?40c to +85c 8-lead msop rm-8 #s6b adg721acpz-reel ?40c to +85c 8-lead lfcsp_wd cp-8-4 17 adg721acpz-reel7 ?40c to +85c 8-lead lfcsp_wd cp-8-4 17 adg722brm ?40c to +85c 8-lead msop rm-8 s7b adg722brm-reel7 ?40c to +85c 8-lead msop rm-8 s7b adg722brmz ?40c to +85c 8-lead msop rm-8 #s7b adg722brmz-reel ?40c to +85c 8-lead msop rm-8 #s7b adg722brmz-reel7 ?40c to +85c 8-lead msop rm-8 #s7b ADG722ACPZ-REEL ?40c to +85c 8-lead lfcsp_wd cp-8-4 s2m ADG722ACPZ-REEL7 ?40c to +85c 8-lead lfcsp_wd cp-8-4 0u adg723brm ?40c to +85c 8-lead msop rm-8 s8b adg723brm-reel ?40c to +85c 8-lead msop rm-8 s8b adg723brm-reel7 ?40c to +85c 8-lead msop rm-8 s8b adg723brmz ?40c to +85c 8-lead msop rm-8 #s8b adg723brmz-reel ?40c to +85c 8-lead msop rm-8 #s8b adg723brmz-reel7 ?40c to +85c 8-lead msop rm-8 #s8b adg723acpz-reel ?40c to +85c 8-lead lfcsp_wd cp-8-4 s2n adg723acpz-reel7 ?40c to +85c 8-lead lfcsp_wd cp-8-4 s2n 1 z = rohs compliant part; # denotes lead-free product may be top or bottom marked. 2 branding = due to package size limitations, the se three characters repr esent the part number.
adg721/adg722/adg723 rev. d | page 15 of 16 notes
adg721/adg722/adg723 rev. d | page 16 of 16 notes ?2004-2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00045-0-4/11(d)

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